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LT1002 Dual, Matched Precision Operational Amplifier
FEATURES
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DESCRIPTION
The LT (R)1002 dual, matched precision operational amplifiers combine excellent individual amplifier performance with tight matching and temperature tracking between amplifiers. In the design, processing, and testing of the device, particular attention has been paid to the optimization of the entire distribution of several key parameters and their matching. Consequently, the specifications of even the low cost commercial grade (the LT1002C) have been spectacularly improved compared to presently available devices. Essentially, the input offset voltage of all units is less than 80V, and matching between amplifiers is consistently beter than 60V (see distribution plot below). Input bias and offset currents, channel separation, common mode and power suply rejections of the LT1002C are all specified at levels which were previsouly attainable only on very expensive, selected grades of other dual devices. Power dissipation is nearly halved compared to the most popular precision duals, without adversely affecting noise or speed performance. A by-product of lower dissipation is decreased warm-up drift. For even better performance in a single precision op amp, refer to the LT1001 data sheet. A bridge signal conditioning application is shown below. This circuit illustrates the requirement for both excellent matching and individual amplifier specifications.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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Guaranteed low offset voltage LT1002A 60V max LT1002 100V max Guaranteed offset voltage match LT1002A 40V max LT1002 80V max Guaranteed low drift LT1002A 0.9V/C max LT1002 1.3V/C max Guaranteed CMRR LT1002A 110dB min LT1002 110dB min Guaranteed channel separation LT1002A 132dB min LT1002 130dB min Guaranteed maching characteristics Low noise 0.35V p-p
APPLICATIONS
s s s s s s
Thermocouple Amplifiers Strain Gauge Amplifiers Low level signal processing Medical instrumentation Precision dual limit threshold detection Instrumentation amplifiers
Strain Gauge Signal Conditioner with Bridge Excitation
+15V +15V 8.2k 2.0K* 4 4.99k* 100 5W
+
1
LM329
/2LT1002
13 2k IN4148
2N2219
REFERENCE OUT TO MONITORING A/D CONVERTER
3
NUMBER OF UNITS
-
3 350 BRIDGE * 301k 10k ZERO 2
+
LT1001 6 1F 0 TO 10V OUT 340k*
-
10
-
1
IN4148 /2LT1002 6 2N2907 2k 100 5W *RN60C FILM RESISTORS -15V
GAIN TRIM
1.1k*
11
+
1002 TA01
U
U
Distribution of Offset Voltage Match
70 60 50 40 30 20 10
VS = 15V TA = 25C 287 UNITS TESTED
0 -100 -80 -60 -40 -20 0 20 40 60 80 100 INPUT OFFSET VOLTAGE MATCH (V)
1002 TA02
1
LT1002
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Note 6)......................................... 22V Differential Input Voltage ...................................... 30V Input Voltage Equal to Supply Voltage Output Short Circuit Duration ......................... Indefinite Operating Temperature Range LT1002AM/LT1002M ....................... - 55C to 125C LT1002AC/LT1002C ............................... 0C to 70C Storage Temperature Range All Grades ......................................... - 65C to 150C Lead Temperature (Soldering, 10 sec.)................. 300C
PACKAGE/ORDER INFORMATION
TOP VIEW NULL (A) 1 NULL (A) 2 -IN (A) 3 +IN (A) 4 V- (B) 5 OUT (B) 6 V+ (B) 7 J PACKAGE 14 PIN HERMETIC
-
14 V+ (A) 13 OUT (A) A
+
ORDER PART NO. LT1002AMJ LT1002MJ LT1002ACJ LT1002CJ LT1002ACN LT1002CN
12 V- (A)
+
B
-
11 +IN (B) 10 -IN (B) 9 NULL (B) 8 NULL (B)
OFFSET VOLTAGE MAX at 25C 60V 100V 60V 100V 60V 100V
N PACKAGE 14 PIN PLASTIC
NOTE: Device may be operated even if insertion is reversed; this is due to inherent symmetry of pin locations of amplifiers A and B. (Note 6)
ELECTRICAL CHARACTERISTICS, I DIVIDUAL A PLIFIERS
VS = 15V, TA = 25C, unless otherwise noted
SYMBOL VOS VOS Time IOS IB en en AVOL CMRR PSRR Rin VOUT SR GBW Pd PARAMETER Input Offset Voltage Long Term Input Offset Voltage Stability Input Offset Current Input Bias Current Input Noise Voltage Input Noise Voltage Density Large Signal Voltage Gain Common Mode Rejection Ratio Power Supply Rejection Ratio Input Resistance Differential Mode Input Voltage Range Maximum Output Voltage Swing Slew Rate Gain Bandwidth Product Power Dissipation per amplifier RL 2k RL 1k RL 2k (Note 4) Note 4 No load No load, VS = 3V 0.1Hz to 10Hz (Note 2) fO = 10Hz (Note 5) fO = 1000Hz (Note 2) RL 2k, VO = 12V RL 1k, VO = 10V VCM = 13V VS = 3V to 18V Note 4 400 250 110 108 20 13 13 12 0.1 0.4 CONDITIONS Note 1 Notes 2 and 3 LT1002AM/LT1002AC MIN TYP MAX 20 60 0.3 0.3 0.6 0.35 10.3 9.6 800 500 126 123 100 14 14 13.5 0.25 0.8 46 4 75 7 1.5 2.8 3.0 0.7 20.0 11.5 350 220 110 105 13 13 13 12 0.1 0.4 LT1002M/LT1002C MIN TYP MAX 25 100 0.4 0.4 0.7 0.38 10.5 9.8 800 500 126 123 80 14 14 13.5 0.25 0.8 48 4 85 8 2.0 4.2 4.5 0.75 20.0 12.0 UNITS V V/month nA nA Vp-p nVHz V/mV dB dB M V V V/s MHz mW
2
U
W
U
W
U
U
WW
W
LT1002
ELECTRICAL CHARACTERISTICS, I DIVIDUAL A PLIFIERS
VS = 15V, - 55C TA 125C, unless otherwise noted
SYMBOL VOS VOS Temp IOS IB AVOL CMRR PSRR VOUT Pd PARAMETER Input Offset Voltage Average Input Offset Voltage Drift Input Offset Current Input Bias Current Large Signal Voltage Gain Common Mode Rejection Ratio Power Supply Rejection Ratio Input Voltage Range Output Voltage Swing Power Dissipation per amplifier RL 2k No load RL 2k, VO = 10V VCM = 13V VS = 3V to 18V CONDITIONS Note 1 MIN
q q q q q q q q q q
LT1002AM TYP MAX 30 150 0.2 0.8 1.0 0.9 5.6 6.0
300 106 102 13
12.5 13.5 55 90
VS = 15V, 0C TA 70C, unless otherwise noted
SYMBOL VOS VOS Temp IOS IB AVOL CMRR PSRR VOUT Pd PARAMETER Input Offset Voltage Average Input Offset Voltage Drift Input Offset Current Input Bias Current Large Signal Voltage Gain Common Mode Rejection Ratio Power Supply Rejection Ratio Input Voltage Range Output Voltage Swing Power Dissipation per amplifier RL 2k No Load RL 2k, VO = 10V VCM = 13V VS = 3V to 18V CONDITIONS Note 1 MIN
q q q q q q q q q q
LT1002AC TYP MAX 20 100 0.2 0.5 0.7 0.9 4.2 4.5
350 108 105 13
12.5 13.8 50 85
The q denotes the specifications which apply over the full operating temperature range. For MIL-STD components, please refer to LTC 883C data sheet for test listing and parameters. Note 1: Offset voltage measured with high speed test equipment, approximately 1second after power is applied. Note 2: This parameter is tested on a sample basis only. Note 3: Long Term Input Offset Voltage Stability refers to the averaged trend line of VOS versus Time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5V.
Note 4: Parameter is guaranteed by design. Note 5: 10Hz noise voltage density is sample tested on every lot. Devices 100% tested at 10Hz are available on request. Note 6: The V + supply terminals are completely independent and may be powered by separate supplies if desired (this approach, however, would sacrifice the advantages of the power supply rejection ratio matching). The V - supply terminals are both connected to the common substrate and must be tied to the same voltage. Both V - pins should be used.
W
14
U
MIN
LT1002M TYP MAX 45 230 0.3 1.2 1.5 1.3 8.5 9.0
UNITS V V/C nA nA V/mV dB dB V V
700 122 117
200 104 96 13 12.0
700 120 117 14 13.5 60 100
mW
MIN
LT1002C TYP MAX 30 160 0.3 0.6 1.0 1.3 5.7 6.0
UNITS V V/C nA nA V/mV dB dB V V
750 124 120 14
250 106 100 13 12.5
750 123 120 14 13.8 55 90
mW
3
LT1002
ATCHI G CHARACTERISTICS at VS = 15V, TA = 25C, unless otherwise noted
PARAMETER Input Offset Voltage Match Average Non-Inverting Bias Current Non-Inverting Offset Current Inverting Offset Current Common Mode Rejection Ratio Match Power Supply Rejection Ratio Match Channel Seperation VCM = 13V VS = 3V to 18V f 10Hz (Note 4) CONDITIONS LT1002AM/AC MIN TYP MAX - 15 40 - - - 110 108 132 0.6 0.6 0.6 132 130 148 3.5 3.5 3.5 - - - MIN - - - - 108 102 130 LT1002M/C TYP MAX 25 80 0.7 0.7 0.7 132 128 146 4.8 6.0 6.0 - - - UNITS V nA nA nA dB dB dB
SYMBOL IB+ IOS+ IOS- CMRR PSRR
ATCHI G CHARACTERISTICS at VS = 15V, - 55C TA 125C, unless otherwise noted
PARAMETER Input Offset Voltage Match Input Offset Voltage Tracking Average Non-Inverting Bias Current Non-Inverting Offset Current Inverting Offset Current Common Mode Rejection Ratio Match Power Supply Rejection Ratio Match VCM = 13V VS = 3V to 18V CONDITIONS
q q q q q q q
SYMBOL
IB
+
IOS+ IOS- CMRR PSRR
ATCHI G CHARACTERISTICS at VS = 15V, 0C TA 70C, unless otherwise noted
PARAMETER Input Offset Voltage Match Input Offset Voltage Tracking Average Non-Inverting Bias Current Non-Inverting Offset Current Inverting Offset Current Common Mode Rejection Ratio Match Power Supply Rejection Ratio Match VCM = 13V VS = 3V to 18V CONDITIONS
q q q q q q q
SYMBOL
IB
+
IOS+ IOS- CMRR PSRR
4
U U U
W W W
MIN - - - - - 106 102
LT1002AM TYP MAX 50 140 0.3 1.5 1.5 1.5 126 122 1.0 6.0 6.5 6.5
MIN - - - - - 102 94
LT1002M TYP MAX 60 230 0.4 1.8 1.8 1.8 124 120 1.5 10.0 12.0 12.0 - -
UNITS V V/C nA nA nA dB dB
MIN - - - - -
LT1002AC TYP MAX 30 85 0.3 1.0 1.0 1.0 130 126 1.0 4.5 5.0 5.0 - -
MIN - - - - - 105 98
LT1002C TYP MAX 45 150 0.4 1.2 1.2 1.2 128 124 1.5 7.0 8.5 8.5 - -
UNITS V V/C nA nA nA dB dB
108 105
LT1002 TYPICAL PERFORMANCE CHARACTERISTICS
Distribution of Offset Voltage of Individual Amplifiers
100
VS = 15V TA = 25C 574 UNITS TESTED
NUMBER OF UNITS
80
NUMBER OF UNITS
60
40 30 20 10
NUMBER OF UNITS
40
20
0 -100 -80 -60 -40 -20 0 20 40 60 80 100 INPUT OFFSET VOLTAGE (V)
1002 G01
Offset Voltage Drift with Temperature of Six Representative Units
INDIVIDUAL AMPLIFIER OFFSET VOLTAGE (V)
80
OFFSET VOLTAGE MATCH (V)
80
VS = 15V LT1002M LT1002AM
LT AM 1002
CHANGE IN OFFSET VOLTAGE (MICROVOLTS)
100
60 40 20 0 -20 -40 -60 -80 -100 -50 -25 LT1002M
LT1 002AM
LT1002M LT1002AM
LT10 02AM
LT1002M
50 25 0 75 TEMPERATURE (C)
Long Term Stability of Four Representative Units
10
OFFSET VOLTAGE CHANGE (V)
VOLTAGE NOISE nV/Hz
30
1/f CORNER 4Hz VOLTAGE
3
0
10
1
-5
3
1/f CORNER 70Hz CURRENT
0.3
-10
0
1
3 2 TIME (MONTHS)
4
5
1001 G07
0
2
6 4 TIME (SECONDS)
8
10
1001 G08
1 1 10 100 FREQUENCY (Hz)
0.1 1000
1002 G09
5
CURRENT NOISE pA/Hz
5
NOISE VOLTAGE 100nV/DIV
UW
100
1002 G04
Distribution of Offset Voltage Drift with Temperature (Individual Amplifiers)
70 60 260 UNITS TESTED 50 25 20 15 10 5 VS = 15V 35 30
Distribution of Offset Voltage Match Drift with Temperature
VS = 15V 130 UNITS TESTED
0 -1.2
0 +0.4 +0.8 +1.2 -0.8 -0.4 INPUT OFFSET VOLTAGE DRIFT WITH TEMPERATURE (V/C) 1002 G02
-1.2
0 +0.4 +0.8 +1.2 -0.8 -0.4 OFFSET VOLTAGE MATCH DRIFT WITH TEMPERATURE (V/C) 1002 G03
Offset Voltage Tracking with Temperature of Six Representative Units
100
Warm-Up Drift
5 VS = 15V TA = 25C N14 PLASTIC PACKGE
60 40 20 0 -20 -40 -60 -80
4
3 J14 HERMETIC DIP PACKGE 2
L
2M T100
LT1002AM LT1002M
1
125
-100 -50
0 0 3 4 2 TIME AFTER POWER ON - BOTH AMPLIFIERS (MINUTES) 1 5
1002 G06
-25
50 25 0 75 TEMPERATURE (C)
100
125
1002 G04
0.1Hz to 10Hz Noise
100
Noise Spectrum
10 TA = 25C VS = 3 TO 18V
LT1002 TYPICAL PERFORMANCE CHARACTERISTICS
Matching and Individual Amplifier Bias and Offset Currents vs Temperature
2.0 1.5 VS = 15V 1.0 INPUT BIAS CURRENT (nA)
VCM Ib
INPUT BIAS AND OFFSET CURRENTS (nA)
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
INVERTING OR NON-INVERTING INPUT BIAS CURRENT (mA)
MATCHING: NON INVERTING BIAS CURRENT
M N O ATC N -I H I N G N V . : IN V IV I DU OFFS ERING & AL ET CU AM RRENT IND P BI AS C IV I DU URRE AL A NT MP O FFSET CURRENT
IN D
50 25 75 0 TEMPERATURE (C) 100 125
0 -50 -25
Open Loop Voltage Gain vs Temperature
140
OPEN LOOP VOLTAGE GAIN (V/V)
OPEN LOOP VOLTAGE GAIN (dB)
1200k 1000k 800k 600k 400k 200k 0 -50 -25 VS = 15V, VO = 12V VS = 3V, VO = 1V
80 60 40 20 0
VOLTAGE GAIN (dB)
100 VS = 15V
12 8 4 0 -4 GAIN 125C GAIN 25C & -55C VS = 15V PHASE MARGIN -55C = 63 125C = 57 0.2 1 0.5 FREQUENCY (MHz) 2
1002 G15
120 25C PHASE MARGIN = 60 140 160 180 200 220
VS = 3V
50 25 75 0 TEMPERATURE (C)
100
125
-20 0.1
1
10
100 1k 10k 100k 1M 10M FREQUENCY (Hz)
1002 G14
-8 0.1
1002 G13
Open Loop Gain Mismatch vs Frequency
1.0
OPEN LOOP GAIN MISMATCH (PERCENT)
Closed Loop Output Impedance
100
POWER SUPPLY REJECTION (dB)
Power Supply Rejection and PSRR Match vs Frequency
160 140 120 100 80 60 40 20 0 0.1 10 100 1k FREQUENCY (Hz) 10k 100k NEGATIVE SUPPLY POSITIVE SUPPLY MATCH (POSITIVE SUPPLY) VS = 15V 2V pp TA = 25C MATCH (NEGATIVE SUPPLY)
VS = 15V TA = 25C OUTPUT IMPEDANCE ()
0.8
10 AV = 1000 1 AV = +1 0.1 IO = 1mA VS = 15V TA = 25C 1 10 1k 100 FREQUENCY (Hz) 10k 100k
1002 G17
0.6
0.4 PERCENT GAIN MISMATCH = OUTPUT A - OUTPUT B x 100% 1/2 (OUTPUT A + OUTPUT B)
0.2
0.01
0 1 10 1k 100 FREQUENCY (Hz) 10k 100k
1002 G16
0.001
1
1002 G18
6
PHASE SHIFT (DEGREES)
UW
1001 G10
Input Bias Current Over the Common Mode Range
30
- +
Input Bias Current vs. Differential Input Voltage
VS = 15V TA = 25C
0.5 0 -.5
DEVICE WITH POSITIVE INPUT CURRENT VS = 15V TA = 25C
20
10
DEVICE WITH NEGATIVE INPUT CURRENT -1.0 -1.5 -15 COMMON-MODE INPUT RESISTANCE = 28V = 280G 0.1nA 10 -5 0 5 -10 COMMON-MODE INPUT VOLTAGE 15
IB 1 nA 0 0.1 0.3 1.0 3.0 10 DIFFERENTIAL INPUT (VOLTS) 30
1002 G12
1002 G11
Open Loop Voltage Gain Frequency Response
20
TA = 25C 120
Gain, Phase Shift vs. Frequency
80 PHASE 25C 100 16
LT1002 TYPICAL PERFORMANCE CHARACTERISTICS
Channel Separation vs Frequency
160 150
CHANNEL SEPARATION (dB)
COMMON MODE REJECTION (dB)
140 130 120 110 100
RS =10
120 100 80 60 40 20 0 1 CMRR
MATCH (< CMRR)
COMMON MODE LIMIT (VOLTS) REFERRED TO POWER SUPPLY
RS =100
RS =1k 90 80 100 1k 100k 10k FREQUENCY (Hz) 1M
1002 G19
Supply Churrent vs. Supply Voltage For Each Amplifier
OUTPUT VOLTAGE, PEAK-TO-PEAK (VOLTS)
2.0
SUPPLY CURRENT (mA)
-55C 1.5 125C 1.0
0.5
3
6 9 12 15 18 21 SUPPLY VOLTAGE (V)
1002 G22
Small Signal Transient Response
100
PERCENT OVERSHOOT
AV = +1, CL = 50pF
UW
VS = 15V TA = 25C
Common Mode Rejection and CMRR Match vs Frequency
160 140 VS = 15V TA = 25C
V+ -0.2 -0.4 -0.6 -0.8 -1.0
Common Mode Limit vs Temperature
V + = 1.2 to 4V V + = 12 to 18V
10
100 1k 10k FREQUENCY (Hz)
100k
1M
+1.0 +.8 +.6 +.4 +.2 V- -50 -25
V - = -12 to -18V V - = -1.2 to -4V
50 25 75 0 TEMPERATURE (C)
100
125
1002 G20
1002 G21
Large Signal Transient Response
28 24 20 16 12 8 4 0
1002 G23
Maximum Undistorted Output vs. Frequency
VS = 15V TA = +25C
25C
1
10 100 FREQUENCY (kHz)
1000
1002 G24
Voltage Follower Overshoot vs Capacitive Load
VS = 15V TA = 25C VIN = 100mV RL > 50k
Small Signal Transient Response
80
60
40
20
0 100
1002 G25
10,000 1000 CAPACITIVE LOAD (PICOFARADS)
100,000 AV = +1, CL = 1000pF
1002 G26 1002 G27
7
LT1002 TYPICAL PERFORMANCE CHARACTERISTICS
Output Swing vs. Load Resistance
16
SHORT CIRCUIT CURRENT (mA) SINKING SOURCING
NEGATIVE SWING
OUTPUT SWING (VOLTS)
12
8
4 VS = 15V TA = 25C 0 100 1000 3k 300 LOAD RESISTANCE () 10k
1002 G28
APPLICATIONS INFORMATION
The LT1002 dual amplifier may be inserted directly into OP-10, OP207, OP227 sockets with or without removal of external nulling potentiometers. Offset Voltage Adjustment The input offset voltage of the LT1002, and its drift with temperature, are permanently trimmed at wafer testing to a low level. However, if further adjustment of VOS is necessary, nulling with a 10k or 20k potentiometer will not degrade drift with temperature. Trimming to a value other than zero creates a drift of (VOS/ 300)V/C, e.g. if VOS is adjusted to 300V, the change in drift will be 1V/C. The adjustment range with a 10k or 20k pot is approximately 2.5mV. If less adjustment range is needed, the sensitivity and resolution of the nulling can be improved by using a smaller pot in conjunction with fixed resistors. The example has an approximate null range of 100V. In matching applications, both amplifiers can be trimmed to zero, or the offset of one amplifier can be trimmed to match the offset of the other. Offset adjustment, however, slightly degrades the gain, common-mode and powersupply rejection match between the two op amps. Fortunately, the guaranteed offset voltage match of the LT1002 is very low, in most applications offset adjustment will be unnecessary.
Standard Adjustment
(10) INPUT 4 (11)
Improved Sensitivity Adjustment
1 3 (10) INPUT 4 (11)
8
+
-
+
-
U
W
UW
Output Short Circuit Current vs Time
50 40 30 20 10 -10 -20 -30 -40 -50 0 1 3 2 TIME FROM OUTPUT SHORT (MINUTES) 4 -55C 25C 125C VS = 15V 125C 25C -55C
POSITIVE SWING
1002 G29
U
U
10k or 20k 1 (8) 2 3
+15V
(9) 14 (7) 13 (6) OUTPUT
1/2 LT1002
12 (5) -15V
1002 TA03
7.5k 1k 7.5k (8) 2 (9) 14 +15V
(7) 13 (6) OUTPUT
1/2 LT1002
12 (5) -15V
1002 TA04
LT1002
APPLICATIONS INFORMATION
Test Circuit for Offset Voltage and its Drift with Temperature
*50k +15V
0.1F
(10) 100 * 4 (11) 50k *
12 (5) -15V *RESISTORS MUST HAVE LOW THERMOELECTRIC POTENTIAL.
1002 TA05
VO = 1000 VOS
This circuit is also used as burn-in configuration for the LT1002, with supply voltages increased to 20V. Unless proper care is exercised, thermocouple effects, caused by temperature gradients across dissimilar metals at the contacts to the input terminals, can exceed the inherent drift of the amplifier. Air currents should be minimized, package leads should be short, the two input leads should be as close together as possible and maintained at the same temperature.
Power supplies The LT1002 is specified over a wide range of power supply voltages from 3V to 18V. Operation with lower supplies is possible, down to 1.2V (two Ni-Cad batteries). However, with 1.2V supplies, the device is stable only in closed loop gains of + 2 or higher (or inverting gain of one or higher). The V+ supply terminals are completely independent and may be powered by separate supplies if desired (this approach, however, would sacrifice the advantages of the power supply rejection ratio matching). The V- supply terminals are both connected to the common substrate and must be tied to the same voltage. Both V - pins should be used.
Channel Separation This parameter is defined as the ratio of the change in input offset voltage of one amplifier to the change in output voltage of the other amplifier causing the offset change. At low frequencies the LT1002's channel separation is an almost unmeasurable 148dB. As frequency increases, pin to pin capacitance of the package, between the output of one amplifier and the inputs of the other, becomes dominant. Since these pins are non-adjacent, the capacitance is only 0.02pF. To maintain the LT1002's excellent channel separation at higher frequencies, the socket and PC board capacitances should be minimized.
+
-
+
-
3
14 (7) 13 (6)
100k
1/2 LT1002
VO
10 2k
U
W
U
U
0.1Hz to 10Hz Noise Test Circuit
The device under test should be warmed up for three minutes and shielded from air currents. Turn the device 180 to measure the noise of side B.
VOLTAGE GAIN = 50,000
1/2 LT1002
A 4.7 F
+
1/2 LT1002
4.3k
22F SCOPE x1 RIN = 1M 110k
DEVICE UNDER TEST
-
B 100k 2.2F
24.3k
0.1 F
1002 TA06
(Peak to Peak noise measured in 10 Sec interval)
9
LT1002
APPLICATIONS INFORMATION
Advantages of Matched Dual Op Amps In many applications the performance of a system depends on the matching between two operational amplifiers rather than the individual characteristics of the two op amps. Two or three op amp instrumentation amplifiers, tracking voltage references and low drift active filters are some of the circuits requiring matching between two op amps. The well-known triple op amp configuration illustrates these concepts. Output offset is a function of the difference between the offsets of the two halves of the LT1002. This error cancellation principle holds for a considerable number of input referred parameters in addition to offset voltage and its drift with temperature. Input bias current will be the average of the two non-inverting input currents (IB+). The difference between these two currents (IOS+) is the offset current of the instrumentation amplifier. The difference between the inverting input currents (IOS-) will cause errors flowing through R1, R2, and R3. Commonmode and power supply rejections will be dependent only on the match between the two amplifiers (assuming perfect resistor matching). The concepts of common mode and power supply rejection ratio match (CMRR and PSRR) are best demonstrated with a numerical example: Assume CMRRA = + 1.0V/V or 120dB, and CMRRB = + 0.75V/V or 122.5dB, then CMRR = 0.25V/V or 132dB; if CMRRB = - 0.75V/V which is still 122.5dB, then CMRR = 1.75V/V or 115dB. Clearly, the LT1002, by specifying and guaranteeing all of these matching parameters, can significantly improve the performance of matching dependent circuits.
Three Op Amp Instrumentation Amplifier
-
10
U
W
U
U
INPUT
+
A
1/2 LT1002
R4 10k 1% 100 1%
R6 10k 1%
-
R1
R3
2.1k 1% 200
-
R10 100k C1 100pF LT1037 OUTPUT
R8
+
-
INPUT
R2 B
10k 1% R5 100 1% 9.76k 1% 200
Gain = 1000
1/2 LT1002
+
+
R7 R9
1002 TA07
Trim R8 for gain Trim R9 for DC common mode rejection Trim R10 for AC common mode rejection
Typical performance of the instrumentation amplifier: Input offset voltage = 25V Input bias current = 0.7nA Input resistance = 200 G Input offset current = 0.6nA Input noise = 0.5V p-p Power bandwidth (V0 = 10V) = 80kHz
LT1002
APPLICATIONS INFORMATION
Precision 10V Reference
+15V 130k 5%
4
+ -
1/2 LT1002
3 LM129A
8.2k 1%
1k
The LT1002 contributes less than 5% of the total drift with temperature, noise and long term drift of the reference.
Dual Limit Microvolt Comparator
+15V 39.2 1% 1k 5% FLV117 15k 1%
1/4 CA3118
14 UPPER LIMIT 3
-
1/2 LT1002
4
+
12 -15V
INPUT 430k 10 7 1% 8 6
-
1/2 LT1002
LOWER LIMIT
11
+
5 -15V
When the upper or lower limit is exceeded the LED lights up. Positive feedback to one of the nulling terminals creates 5 to 20V of hysteresis on both amplifiers. This
U
14 12
1
W
U
U
3.3k 1% 10k 0.1% 13 10k 0.1% 11 3.3k 1% -15V 10
OUT 1 10.000V
- +
7 6 OUT 2 -10.000V
1/2 LT1002
5
1002 TA08
The accuracy of the -10V output is limited by the matching of the two 10k resistors.
430k 1% 13
20k 5%
1/4 CA3118
39.2 1%
15k 1%
1/4 CA3118
1/4 CA3118
1002 TA09
feedback changes the offset voltage of the LT1002 by less than 5V. Therefore, the basic accuracy of the comparator is limited only by the low offset voltage of the LT1002.
11
LT1002
APPLICATIONS INFORMATION
Two Op Amp Instrumentation Amplifier
R5 2.2k+ R1 100k* R2 10k R4 100k
-
1/2 LT1002
-
INPUTS
+
+
* TRIM FOR COMMON-MODE REJECTION + TRIM FOR GAIN Gain = R4 1 1+ R3 2
(
R2 R3 R2 + R3 + + 100 R1 R4 R5
Precision Amplifier Drives 500 Load to 10V
1.1Rf + 0.1RS 110k RS 100 +15
-
B 1/2 LT1002 -15V Rf 100k 100 0.2RL
+
RS 100
-
A
+15V OUTPUT 500 RL
1/2 LT1002
+
INPUT
-15V
1002 TA11
12
U
W
U
U
R3 10k
-
1/2 LT1002
OUTPUT
+
1002 TA10
)
This application utilizes the guaranteed 10mA load driving capability of the LT1002. The offset voltage of amplifier A is the offset of the configuration. Amplifier B provides the additional 10mA load current. When load resistor RL is removed, amplifier A sinks this current without affecting accuracy. In the gain of 1000 configuration shown, approximately 0.3% gain accuracy can be realized.
LT1002
APPLICATIONS INFORMATION
Dead Zone Generator
INPUT ** 100k ** 100k 2 Q4 10k* Q2 6 8 1 3 2N4393 Q1 30pF 4.7k 10k* 2k Q3 VSET DEAD ZONE CONTROL INPUT 0 to 5V BIPOLAR SYMMETRY IS EXCELLENT BECAUSE ONE DEVICE, Q2, SETS BOTH LIMITS
-
LM301A
3 100k
+
IN914 +15V 100k 15pF 2 4.7k
-
LM301A 6
4.7k Q5 1k
3
+
-15V
Precision Absolute Value Circuit
INPUT -10 to 10V
10k 0.1%
3
-
1/2 LT1002
4
+
IN4148 10k
0.1%
U
W
U
U
47pF
-
1/2 LT1002
10k** 13 10k** 10 10k 10k 2N4393 Q6
-
1/2 LT1002
4
+
15pF
6
VOUT
11
+
3.3k
IN914 VSET VOUT VIN VSET
* 1% FILM ** RATIO MATCH 0.05% Q2, 3, 4, 5 CA 3096 TRANSISTOR ARRAY
1002 TA12
10k 0.1% IN4148 13
10k 0.1% 10
10k 0.1%
-
1/2 LT1002
6
OUTPUT 0 to 10V
11
+
1002 TA13
13
LT1002
APPLICATIONS INFORMATION U W U
3 4 8.2k TRIAD TY-90 VN-46 LM399 DIODES = SEMTECH # FF-15 6 33k 74C74 33k +15 33k +15V 1.8k CLAMP SET 5k IN914
1002 TA14
100
43k* (select)
+15V
-15V KVD= ESI#DP311 *= JULIE RSCH. LABS #R-44 25k 680pF 2
-
LT301A
3
+
14
U
22k*
+15 100 5W 2k 13 IN914 2N2219
-
1/2 LT1002
Dual Precision Power Supply (1) 0 to 10V in 100V Steps (2) 0 to 100V in 1mV Steps
OUTPUT 1 0-10V 25mA
+
KVD 00000 - 99999 + 1 KELVIN-VARLEY DIVIDER ESI#DP311 VN-46
+
4 90k*
OUTPUT 2 0-100V, 25mA
0.1
+
D CLK Q Q
2.2
10k* (select) TRIM-100V 100
2N6533 2k 6 IN914 15 +15 2N2907
-
1/2 LT1002
10
+
22f
+
11
LT1002
SCHE ATIC DIAGRA
V+ 6k 6k
NULL
40k
NULL 40k
Q5 Q7 Q3
Q6 Q8 Q4 55pF 3k Q31 20pF Q33 20
+
IN
500
Q1A
Q1B
Q2B
-
IN
Q10 500 T1 2k 180
1/2 LT1002
Q9 V- Q19
PACKAGE DESCRIPTION
N Package 14-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770* (19.558) MAX 14 13 12 11 10
0.255 0.015* (6.477 0.381)
1 0.300 - 0.325 (7.620 - 8.255) 0.130 0.005 (3.302 0.127) 0.015 (0.380) MIN 0.009 - 0.015 (0.229 - 0.381)
2
3
0.045 - 0.065 (1.143 - 1.651)
0.005 (0.125) +0.635 8.255 MIN -0.381 0.100 0.010 (2.540 0.254) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
(
+0.025 0.325 -0.015
)
0.125 (3.175) MIN
TJMAX LT1002ACN LT1002CN 125C
JA 100C/W
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
W
Q27 Q28 1.5k Q11 Q13 Q14 Q12 25k Q29 Q24 Q25 Q2A 30pF 3k Q21 Q16 Q15 Q22 2k Q18 Q23 Q34 Q26 OUT 20 Q32 Q20 Q17 Q30 8k 120 240
1002 SS
W
Dimensions in inches (millimeters) unless otherwise noted. J Package 14-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-1110)
CORNER LEADS OPTION (4 PLCS) 0.005 (0.127) MIN 0.785 (19.939) MAX 14 13 12 11 10 9 8
9
8
0.023 - 0.045 (0.584 - 1.143) HALF LEAD OPTION 0.045 - 0.068 (1.143 - 1.727) FULL LEAD OPTION
0.025 (0.635) RAD TYP
0.220 - 0.310 (5.588 - 7.874)
1 0.300 BSC (0.762 BSC)
2
3
4
5
6
7
4
5
6
7
0.200 (5.080) MAX 0.015 - 0.060 (0.381 - 1.524)
0.065 (1.651) TYP 0.018 0.003 (0.457 0.076)
N14 0695
0.008 - 0.018 (0.203 - 0.457) 0.385 0.025 (9.779 0.635)
0 - 15
0.045 - 0.068 (1.143 - 1.727) 0.014 - 0.026 (0.360 - 0.660)
0.100 0.010 (2.540 0.254)
0.125 (3.175) MIN
J14 0694
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP OR TIN PLATE LEADS.
TJMAX LT1002ACJ LT1002CJ LT1002AMJ LT1002MJ 125C 125C
JA 100C/W 100C/W
15
LT1002
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
LT/GP 0396 2K REV A * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1985

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